Field of the Invention
Embodiments of the present invention relate generally to integrated circuit chip packaging and, more specifically, to a chip package using an interposer substrate with through-silicon vias.
Description of the Related Art
In the packaging of integrated circuit (IC) chips, it is generally desirable to minimize the size and thickness of the packaging assembly, or “chip package,” in which an IC chip is encased. In mobile computing devices, such as smart phones, laptop computers, electronic tablets, and the like, it is particularly desirable to minimize the thickness of IC packages, so that such mobile devices can be further reduced in size and weight. For example, rather than being mounted on a conventional packaging substrate, which has a thickness on the order of one or more millimeters, IC chips can be mounted on an interposer substrate, which may be as thin as 100 microns.
However, interposer substrates are prone to significant warpage when used as part of a chip package, particularly during the reflow process. Warpage of the interposer substrate during fabrication of a chip package can reduce yield and result in poor package reliability, both of which are highly undesirable.
Accordingly, there is a need in the art for an IC package that has a reduced thickness.